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rev. 1.00 1 december 21, 2016 rev. 1.00 pb december 21, 2016 BC2102 sub-1ghz ook/fsk transmitter features ? operating voltage: ? v dd =2.2v~3.6v@ta= -40 c~+85c ? complete sub-1ghz ook/fsk transmitter ? frequency bands: 315mhz, 433mhz, 868mhz, 915mhz ? supports ook/fsk modulation ? supports 2-wire i 2 c interface ? low sleep current ? tx current consumption@433mhz: ? 17ma (fsk, 10dbm)/1 1ma (ook, 10dbm, 50% duty cycle) ? programmable symbol rate ? on-chip full range vco and fractional-n pll synthesizer ? supports 16/24 mhz low cost crystal ? 4-steps programmable tx power: 0/5/10/13 dbm ? fully integrated vco, on chip loop flter and pll synthesizer ? hardware control mode C mcu not required for radio control ? integrated 64 1-bit fuse data memory ? auto calibration function ? package type: 8-pin sop-ep abbreviation notes tx: rf transmitter sx: synthesizer xo: external crystal pa: power amplifer ook: on-off keying fsk: frequency shift keying vco: voltage control oscillator pll: phase lock loop mmd: multi-mode divider xtal: external crystal general description the BC2102 is a highly integrated ook/fsk transmitter for remote wireless applications. the transmitter is a true "data-in, antenna-out" monolithic device making it very easy for users to implement wireless systems. the BC2102 can operate at the 315mhz, 433mhz, 8 68mhz and 915mhz freq u en cy bands. it supports b o th ook and fsk modulation schemes an d can operate with symbol rate up to 25kbps and 50kbps respectively. BC2102 offers a programmabl e output power level. it is capable of delivering +13dbm maximum power into a 50 load. the BC2102 adopts an agile state machine to ea se the cont rol and mi nimize the powe r consumption. with an external crystal and a few external components, BC2102 can implement a complete solution for an effective rf transmitter. these features can be easily programmed through i 2 c interface or internal fuse. with these combined features the BC2102 can provide a power-saving and cost effective solution for a huge range of remote wireless applications.
rev. 1.00 2 december 21, 2016 BC2102 block diagram freq synth rfout vss pa ramp control fuse data memory vdd din pclk gnd digital interface ldo band gap i 2 c and digital logic xoscin xosc dvdd modulator v12o pin assignment BC2102 8 sop-ep-a dvdd rfout v12o din/sda/icpda xoscin vss pclk/scl/icpck vdd 1 2 3 4 8 7 6 5 pin description pin no. pin name function type description 1 rfout pa_out ao rf output signal from power amplifer connect to matching circuit 2 vss pa_gnd pwr analog negative power supply, ground 3 vdd vdd pwr analog positive power supply 4 xoscin crystal ai external crystal input 5 pclk/scl/ icpck pclk i clock input scl i i 2 c clock input icpck i icp clock input pin 6 din/sda/ icpda din i rf transmitter data input sda i i 2 c data input icpda i icp data input pin 7 v12o ldo_out pwr 1.2v ldo output 8 dvdd vdd pwr digital positive power supply 9 gnd ground pwr expose pad note: i: digital input o: digital output ai: analog input ao: analog output pwr: power
rev. 1.00 3 december 21, 2016 BC2102 *this device is esd sensitive. hbm (human body mode) is based on the mil-std-883h method 3015.8. note: these are stress ratings only. stresses exceeding the range specifed under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those has listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c , v dd =3.3v, f xtal =16 mhz, ook/fsk modulation with matching circuit, paout is powered by v dd =3.3v, unless otherwise noted. ta=25 c symbol parameter description min. typ. max. unit v dd operating voltage 2.2 3.3 3.6 v t op operating temperature -40 85 c v ih high level input voltage 0.7v dd v dd v v il low level input voltage 0 0.3v dd v v oh high level output voltage @i oh = -5ma 0.8v dd v dd v v ol low level output voltage @i ol = 5ma 0 0.2v dd v i sleep current consumptions 0.1 a i standby xtal on, pa off, synthesizer on 6.5 ma i h high data current consumption @315mhz band (data=1) p rf = 0dbm 11 ma p rf = 10dbm 20 p rf = 13dbm 26 high data current consumption @433mhz band (data=1) p rf = 0dbm 11 ma p rf = 10dbm 17 p rf = 13dbm 22 high data current consumption @868mhz band (data=1) p rf = 0dbm 12 ma p rf = 10dbm 19 p rf = 13dbm 25 high data current consumption @ 915mhz band (data=1) p rf = 0dbm 12 ma p rf = 10dbm 19 p rf = 13dbm 25 absolute maximum ratings supply voltage ........................... v ss -0.3v to v ss +3.6v voltage on i/o pins ................... v ss -0.3v to v dd +0.3v esd hbm .......................................................... 2kv storage temperature .......................... -55c to 150c operating temperature ........................ -40c to 85c
rev. 1.00 4 december 21, 2016 BC2102 a.c. characteristics rf characteristics ta=25 c symbol parameter condition min. typ. max. unit rf f rf rf operating frequency range 315 mhz 433 868 915 xtal f xtal rf operating xtal frequency 16 24 mhz esr xtal equivalent series resistance 100 c l xtal capacitor load 16 pf xtal tolerance (1) 20 ppm t startup xtal startup time (2) 1 ms pll f step rf frequency synthesizer step 0.5 khz pn pll 433mhz pll phase noise phase noise @ 100k offset -80 dbc/hz phase noise @ 1m offset -104 868mhz pll phase noise phase noise @ 100k offset -70 phase noise @ 1m offset -100 f dev frequency deviation f xtal = 16mhz 2 100 khz tx sr symbol rate ook modulation 0.5 25 kbps fsk modulation (@f dev =12.5khz) 0.5 50 p rf rf transmitter output power 433mhz 0 13 dbm 868mhz 0 13 t st rf transmitter settling time pll to transmit 370 s er ook ook extinction ratio ook modulation depth 70 db occupied bandwidth (ook, -20dbc) @315mhz 400 khz @433mhz @868mhz @915mhz output blanking time from sleep to rf out 1 ms one shot delay time ook/fsk 4 32 ms se tx transmitter spurious emission (pout =10dbm) f < 1ghz -36 dbm 47mhz < f < 74mhz 87.5 mhz < f < 118mhz 174mhz < f < 230mhz 470mhz < f < 790mhz -54 2 nd , 3 rd harmonic -30 note: 1. this is the total tolerance including (1) initial tolerance (2) crystal loading (3) aging and (4) temperature dependence. the acceptable crystal tolerance depends on rf frequenc and channel spacing/band width. 2. depend on crystal property.
rev. 1.00 5 december 21, 2016 BC2102 functional description the fully integrated rf transmitter can operate in the 315mhz, 433mhz, 868mhz and 915mhz frequency bands. the additional of a crystal and a limited number of external components are all that is required to create a complete and versatile rf transmitter system. the device includes an internal power amplifer and is capable of delivering up to +13dbm into a 50 load. such a power level enables a small form factor transmitter to operate near the maximum transmission regulation limits. the device can operate with ook and fsk receiver types. the fsk data rate is up to 50kbps, allowing the device to support more complicated control protocols. solution overview to provide extra user conveniences, the BC2102 contains an area of fuse memory, which is a kind of popular one-time programming non-volatile memory. if the fuse is un-programmed, which can be detected by checking the efpgm bit in the cfg7 register, the user should connect the device to an mcu and setup the relevant rf registers configuration in the i 2 c mode using an i 2 c interface. the device can operate properly after returning to the normal mode. however, the registers will be reset to their initial state when the device is powered off. for devices whose fuse is programmed, users can implement a complete and versatile rf transmitter system to work together with an external mcu or encoder. the corresponding application solutions are shown as below. note that when efpgm bit is low the device can only be connected to an external mcu. if the device is connected with an encoder, the fuse data will be automatically copied to the corresponding registers. after a delay time, the encoder can send data to the device through the din pin and thus start a transmission sequence. if the device is connected to an mcu, the same function aforementioned can also be implemented. the difference is that the mcu can configure the frequency, power and other parameters by setting the relevant registers using an i 2 c interface when operating in the i 2 c mode. crystal 16/24mhz vdd gnd push button din 2.2v~3.6v power supply pclk BC2102 transmitter matching circuit encoder v12o vdd gnd BC2102 transmitter mcu pclk din v12o 2.2v~3.6v power supply matching circuit crystal 16/24mhz push button
rev. 1.00 6 december 21, 2016 BC2102 sleep state din 10s pa out low transmit valid tx data stop sleep low rf signal t startup t st high tx enabled by din pin state control the BC2102 has integrated state machines that control the state transition between modes. din keep high & pclk low(>16us) detect high edge power off after power up vdd (insert the battery) power on state normal mode din lh or pclk hl copy fuse data to register yes no deep sleep transmitting standby & time on transmit done & din h l 4~32ms timer times up copy finish toff [3:0]=f & din lh check efpgm=1 por procedure i 2 c mode {din keep high & pclk low(>16us) detect high edge} or i 2 c time out(20ms) l 2 c mode state machine when connected with mcu power off after power up vdd (insert the battery) power on state normal mode din l h or pclk hl copy fuse data to register yes no deep sleep transmitting standby & time on transmit done & din hl 4~32ms timer times up copy finish toff[3:0]=f & din l h check efpgm=1 por procedure state machine when connected with encoder power on state after power-on, perhaps by the insertion of a battery, if the efpgm bit state is high, the fuse data will be automatically copied to the corresponding registers. when completed the device will enter the deep sleep mode after a por delay time. note that the device will directly enter the deep sleep mode after a delay time if the efpgm bit is low. normal mode after a power-on reset operation, the device enters the deep sleep mode. data will be transmitted if the din pin is pulled high or the pulse on the pclk pin changes from high to low. when data transmission is fnished and the din pin state changes from high to low, the device will enter the standby state and the timer, whose timeout period is determined by dly_ toff bits in the cfg1 register, will turn on and start to count. the device will return to the deep sleep mode when the timer overfows. however, it should be noted that when the dly_toff[3:0] bit value is "1111", the device will start to transmit again without entering the deep sleep mode once the din pin state changes from low to high.
rev. 1.00 7 december 21, 2016 BC2102 i 2 c mode if the device is connected to an external mcu, then the i 2 c mode can be used. when the scl line (pin 5) is pulled low for more than 16 s (t eni2c ), the device will enter the i 2 c mode from the normal mode, dur - ing which the external control register can confgure the special function registers in the device using i 2 c commands. when the device receives a correct i 2 c stop signal followed by the scl line being pulled low for more than 16 s, the device will return to the normal mode. in the i 2 c mode, the mcu can confgure the internal relevant registers using i 2 c serial programming. the transmitter only supports the i 2 c format for byte write, page write, byte read and page read format. the transmission procedure is shown as below. symbol defnition: ? s: start symbol ? rs: repeat start ? p: stop symbol ? daddr[6:0]: device address, 21h ? r/w: read write select, r(0): write, (1): read ? raddr[7:0]: register address ? ack: a(0):ack, na(1):nak ? bus direction: host to device: device to host: i 2 c ser ia l pr ogra mming nor ma l mode into i 2 c mode i 2 c mode ter minate i 2 c star t co ndition ack i 2 c stop conditio n > 16s t eni 2 c t exi2c > 16s pclk / scl din/sda i 2 c serial programming s daddr[6:0] w a raddr[7:0] a data a p byte write s daddr[6:0] w a raddr[7:0] a data a p page write data(n+1) a data(n+x) a s daddr[6:0] w a raddr[7:0] a daddr[6:0] p byte read a data rs r na s daddr[6:0] w a raddr[7:0] a page read daddr[6:0] a data(n) rs r a data(n+1) a data(n+x) p na
rev. 1.00 8 december 21, 2016 BC2102 scl 0 0 0 0 1 1 0 1 sda start slave addres srw 0 0 0 1 1 1 data ack 0 0 stop scl sda s = start (1 bit) sa = slave address (7 bits) sr = srw bit (1 bit) m = slave device send acknowledge bit (1 bit) d = data (8 bits) a = ack (rxak bit for transmitter, txak for receiver, 1bit) p = stop (1 bit) s sa sr m d a d a sr sa sr m d a d a p note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or the receive mode where it must implement a dummy read from the simd register to release the scl line. 0 ack i 2 c communication timing diagram programming methodology the device programming interface should utilise an adaptor with an integrated 16mhz crystal. program function pin name pin description icpck pclk (pin5) icp clock icpda din (pin) icp data/address vdd vdd (pin3) dvdd (pin8) power supply vss, ep vss (pin2), exposed-pad ground xtal in (adaptor) xoscin (pin4) ic system clock when programming, the device needs to be located on a socket with a 16mhz crystal connected between pin xoscin and ground. holtek provides an e-link or e-writerpro tool for communication with the pc. between the e-link and the device there are four interconnecting lines, namely vdd, vss, pclk and din pins. * * writer_vdd icpda icpck writer_vss to other circuit vdd/dvdd din pclk vss writer connector signals ic programming pins xoscin 16mhz v12o note: * may be resistor or capacitor C the resistance of * must be greater than 1k and the capaci- and the capaci- and the capaci - tance of * must be less than 1nf.
rev. 1.00 9 december 21, 2016 BC2102 register map when connected to an external mcu, the device can be setup and operated using a series of internal registers. device commands and data are written to and read from the device using its internal i 2 c bus. this list provides a summary of all internal registers. their detailed operation is described under their relevant section in the functional description. address register name bit 7 6 5 4 3 2 1 0 00h cfg0 xo_sel xo_trim[5:0] 01h cfg1 dly_toff[3:0] setting1 02h cfg2 fdev[7:0] 03h cfg3 fsk_sel setting2 txpwr[3:0] 04h cfg4 d_n[5:0] band_sel[1:0] 05h cfg5 d_k[11:4] 06h cfg6 d_k[19:12] 07h cfg7 efpgm setting3 cfg0: confguration control register 0 address bit 7 6 5 4 3 2 1 0 00h name xo_sel xo_trim[5:0] r/w r/w r/w r/w initial value 1 0 1 0 0 0 0 0 bit 7~6 xo_sel : external crystal selection 00: reserved 01: 24mhz x'tal 10: 16mhz x'tal 11: reserved bit 5~0 xo_trim[5:0] : trim value for the internal capacitor load for the crystal xo_trim[5:0] equiv. c l (pf) 0 11.676 4 11.822 8 11.927 12 13.247 16 13.962 17 14.137 18 14.295 20 14.639 24 15.301 28 15.955 32 16.651 36 17.288 40 17.962 44 18.610 48 19.294 52 19.870 56 20.472 60 21.003 63 21.411
rev. 1.00 10 december 21, 2016 BC2102 cfg1: confguration control register 1 address bit 7 6 5 4 3 2 1 0 01h name dly_toff[3:0] setting1 r/w r/w r/w r/w initial value 1 1 1 0 0 0 0 1 bit 7~4 dly_toff[3:0] : transmitter auto power off delay time t = 2ms (dly_toff[3:0]+2) 0000: 4ms 0001: 6ms 0010: 8ms : 1110: 32ms 1111: infnite C never enter the deep sleep mode bit 3~0 setting1: must be [0b0001] cfg2: confguration control register 2 address bit 7 6 5 4 3 2 1 0 02h name fdev[7:0] r/w r/w initial value 0 1 1 0 0 1 1 0 bit 7~0 fdev[7:0]: frequency deviation for fsk when external crystal = 24mhz, fdev = (f dev 2 14 / fxtal); fxtal=12mhz when external crystal = 16mhz, fdev = (f dev 2 15 / fxtal); fxtal=16mhz examples are as follows: default fdev[7:0]=01100110 decimal 102 external crystal = 16mhz f dev (frequency deviation) = fdev (16m / 2 15 ) f dev (frequency deviation) = 102 (16m / 32768) = 49.8khz cfg3: confguration control register 3 address bit 7 6 5 4 3 2 1 0 03h name fsk_sel setting2 txpwr[3:0] r/w r/w r/w r/w initial value 0 1 0 0 1 0 0 0 bit 7 fsk_sel: fsk mode enable 0: ook 1: fsk bit 6~4 setting 2: must be [0b100] bit 3~0 txpwr[3:0]: rf output power the device has several output power values which are 0, 5, 10, and 13 dbm for all temperatures. txpwr[3:0] rf output power txpwr[3:0] rf output power 0000 0dbm 1000 10dbm 0100 5dbm 1100 13dbm
rev. 1.00 11 december 21, 2016 BC2102 cfg4: confguration control register 4 address bit 7 6 5 4 3 2 1 0 04h name d_n[5:0] band_sel[1:0] r/w r/w r/w initial value 0 1 0 1 1 0 0 1 bit 7~2 d_n[5:0]: integer of dividend for mmd bit 1~0 band_sel[1:0] : band frequency coarse control band_sel frequency 00 315mhz 01 433mhz 10 868mhz 11 915mhz note that the band_sel only select an approximate frequency range while the exact frequency value is determined by the d_n and d_k bit felds. cfg5: confguration control register 5 address bit 7 6 5 4 3 2 1 0 05h name d_k[11:4] r/w r/w initial value 0 1 1 1 0 0 0 0 cfg6: confguration control register 6 address bit 7 6 5 4 3 2 1 0 06h name d_k[19:12] r/w r/w initial value 0 0 1 1 1 1 0 1 d_k[19:4]: 16-bit fractional of dividend for mmd d_n&d_k example. xtal=16mhz and tx band =433mhz 1. d_n (433m divider)/16m=54.125 take the integer part d_n=54-32=22 010110 2. d_k (433m divider)/16m=54.125 take the fractional part d_k=0.125 2 20 =131072 0010-0000-0000-0000 3. 24mhz xtal calculation: (433m divider)/(24m/2)=72.16666667 take the integer part d_n=72-32=40 101000 take the fractional part d_k=0.16666667 2 20 =174762 0010-1010-1010-1010 4. the example frequency can be refered in the following table. band_sel frequency divider xtal d_n[5:0] d_k[19:4] 315mhz 315mhz 2 24mhz 010100 1000-0000-0000-0000 16mhz 000111 0110-0000-0000-0000 433mhz 433mhz 2 24mhz 101000 0010-1010-1010-1010 16mhz 010110 0010-0000-0000-0000 433mhz 433.92mhz 2 24mhz 101000 0101-0001-1110-1011 16mhz 010110 0011-1101-0111-0000 868mhz 868mhz 1 24mhz 101000 0101-0101-0101-0101 16mhz 010110 0100-0000-0000-0000 915mhz 915mhz 1 24mhz 101100 0100-0000-0000-0000 16mhz 011001 0011-0000-0000-0000
rev. 1.00 12 december 21, 2016 BC2102 cfg7: confguration control register 7 address bit 7 6 5 4 3 2 1 0 07h name efpgm setting3 r/w r r/w r/w r/w initial value 0 1 0 0 1 0 1 1 bit 7 efpgm : fuse programmed, read only for i 2 c 0: fuse is not programmed C fuse data is not mapped to the confguration register 1: fuse is programmed C fuse data is mapped to the confguration register bit 6~0 setting3 : must be [0b1001011] application circuits 433mhz application example BC2102 xoscin pclk vdd din vss v12o rfout dvdd ep clock in data in matching circuit v dd v dd v dd evaluation board circuit BC2102 xoscin pclk vdd din vss v12o rfout dvdd ep clock in data in matching circuit v dd v dd v dd
rev. 1.00 13 december 21, 2016 BC2102 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/ carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 14 december 21, 2016 BC2102 8-pin sop (150mil) outline dimensions (exposed pad) symbol dimensions in inch min. nom. max. a D 0.236 bsc D b D 0.154 bsc D c 0.012 D 0.020 c' D 0.193 bsc D d D D 0.069 d1 0.059 D D e D 0.050 bsc D e2 0.039 D D f 0.004 D 0.010 g 0.016 D 0.050 h 0.004 D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a D 6.00 bsc D b D 3.90 bsc D c 0.31 D 0.51 c' D 4.90 bsc D d D D 1.75 d1 1.50 D D e D 1.27 bsc D e2 1.00 D D f 0.10 D 0.25 g 0.40 D 1.27 h 0.10 D 0.25 0 D 8
rev. 1.00 15 december 21, 2016 BC2102 copyright ? 2016 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw/en/home.

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